As is well known in the art, by comparing the output of non-volatile memory (NVM) cells with a reference level, different current/voltage levels can be associated with different logical states. Accordingly, a NVM cell's current level may be correlated to the amount of charge stored in a charge storage region of the cell. Prior to the storing of any charge within a charge storage region, the cell may be referred to as “native” or in its “initial” state.
Generally, in order to determine whether an NVM cell is at a specific state, for example erased, programmed, or programmed at one of multiple possible program states within a multi-level cell (“MLC”), the cell's current level is compared to that of a reference cell whose current level is preset at a level associated with the specific state being tested for.
The initial positioning of the different reference levels is accomplished using data extracted from the NVM array during manufacturing. During the manufacturing process, after fabrication, an NVM array may be tested to determine the native current levels of each of its cells. These native current levels may then be used for the presetting of the reference levels.
While native threshold voltage distributions over an entire array may be in the order of 2V or more, the distributions across an array segment may be lower, for example 1V. Thus, establishing a lowest reference voltage to be slightly higher than the highest native threshold voltage of a specific segment within the memory array may result in either a larger or smaller ‘Cycle Margin’ (“CM”—The margin between the initial NVM cell level and the lowest reference level) for cells in other array segments whose NVM cells have native threshold voltages relatively lower or higher than those in the segment which was selected for the preset of the reference cell.
In order to avoid such a difference in ‘Cycle Margin’ for the different segments, a lowest reference voltage level for each of the array's segments may be determined. Hence, the lowest reference voltage for each segment may be determined in respect to the highest native threshold voltage of any cell within that given array segment. Still, a need remains in the field of NVM cells operation for methods, circuits and systems for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array.